1. Field of the Invention
This invention relates to an analog/digital (A/D) converter, and more particularly to an A/D converter having a plurality of analog channels.
2. Description of the Related Art
Various types of A/D converters having a plurality of analog channels are known. FIG. 1A shows the construction of a successive approximation type A/D converter as an example of the above A/D converter in which the number of analog channels is "2", and FIG. 1B shows the timing chart of control signals used in the A/D converter of FIG. 1A.
In FIG. 1A, CH1 and CH2 each denote an analog input terminal. When control signal .phi..sub.AIN1 is set to a high (H) level, selected analog switches P.sub.1 and N.sub.1 are turned on, permitting a potential of analog input terminal CH1 to be supplied to the positive input terminal of comparator 1. Further, when control signal .phi..sub.AIN2 is set to a high (H) level, selected analog switches P.sub.2 and N.sub.2 are turned on, permitting a potential of analog input terminal CH2 to be supplied to the positive input terminal of comparator 1.
A reference potential which is used as a reference for the comparing operation is supplied to negative input terminal of comparator by means of digital/ analog (D/A) converter 2. In this case, comparator effects the comparison operation for one bit (or one cycle of comparison operation) by comparing the potential of analog input terminal CH1 or CH2 selected by the control signal with the reference potential.
After one-bit comparison operation is completed, the comparison result is supplied to controller 3. Controller 3 causes the output of D/A converter 2 to be changed according to the comparison result or whether the comparison result is positive or negative when the compared potentials are not equal to each other. As a result, the potential of the negative input terminal of comparator is changed and then the next comparison operation is effected.
After this, the same operation is repeatedly effected until the compared potentials are determined to be equal to each other. When the compared potentials are set equal to each other, controller 3 supplies a digital value which has been given to D/A converter 2 to output terminal OUT. In this way, the A/D converting operation is effected.
Now, assume that the potential of analog input terminal CH1 is subjected to the A/D conversion and then the potential of analog input terminal CH2 is subjected to the A/D conversion. In this case, as shown by the timing chart of FIG. 1B, a blanking period (in which .phi..sub.AIN1 =.phi..sub.AIN2 =low (L) level) is generally provided between signals .phi..sub.AIN1 and .phi..sub.AIN2. The reason why such a blanking period is provided is that a D.C. current path must be prevented from being created between analog input terminals CH1 and CH2 by simultaneously turning on analog switches P.sub.1 and N.sub.1 and analog switches P.sub.2 and N.sub.2 when signals .phi..sub.AIN1 and .phi..sub.AIN2 are switched from one to the other.
In practice, as shown in FIG. 1A, RC filters 4.sub.1 and 4.sub.2 are generally connected to analog input terminals CH1 and CH2 in order to stabilize the analog input (or suppress noise). Assume now that the potential of analog input terminal CH1 is completed and analog switches P.sub.1 and N.sub.1 are turned off. In this case, parasitic capacitor C.sub.1 (C.sub.2 in FIG. 1A is also a parasitic capacitor) associated with the common terminal (point A) which is the positive input terminal of comparator 1 of FIG. 1A is charged to potential V.sub.AIN1 of analog input terminal CH1. Immediately after analog switches P.sub.2 and N.sub.2 are turned on at timing .phi..sub.AIN2, initial value V.sub.A0 of the potential of the common terminal (point A) can be determined by the capacitive division (charge sharing) of capacitors C.sub.1 and C.sub.EX2 if the impedance of each of analog switches P.sub.2 and N.sub.2 is sufficiently smaller than that of resistor R.sub.2. That is, the following equation can be obtained: ##EQU1##
When the potential of capacitor C.sub.EX2 is changed by the charge sharing, charges are supplied from analog input terminal CH2 to capacitor C.sub.EX2, thereby preventing the potential variation. However, in practice, the potential of the common terminal (point A) cannot be restored to the level of potential V.sub.AIN2 of analog input terminal CH2 before the A/D converting operation is completed, particularly, in a case where the time constant of RC filters 4.sub.1 and 4.sub.2 is large. In this case, the result of the A/D conversion may contain an error. The error may become larger as the potential difference between potentials V.sub.AIN1 and V.sub.AIN2 becomes larger and the capacitance of capacitor C.sub.1 becomes larger with respect to that of capacitor C.sub.EX2.
Basically, it is impossible to eliminate the influence by the charge sharing and therefore it becomes important to suppress the potential variation. That is, the influence by the charge sharing ca be observed in the form of on-channel input current and therefore it is important to suppress the on-channel input current to a minimum and attain the highly precise A/D conversion.